EU launches CMOS research project

Chips that are still smaller and more powerful and consume even less energy than those already in the pipeline today are the focus of a new collaborative research project launched Monday by the European Commission.

The European project, called NANOCMOS, aims to pioneer changes in materials, processes, device architectures and interconnections that will push the limits of semiconductor performance and density further yet. Under the initiative, researchers will focus on next-generation CMOS (complementary metal oxide semiconductor) technology, beginning with the 45-nanometer chip production process and extending to 32- and 22-nanometer processes.

CMOS technology — the most widely used integrated circuit design — is found in almost every electronic product, ranging from handheld devices to mainframe computers.

The Commission has agreed to provide seed capital of €24 million ($29.7 million) for the collaborative research project, which will provide the technological basis for later competition. Participating chip makers and research institutes are expected to match this amount. The Commission is the European Union’s executive body.

In the first phase of the project, expected to last 27 months, researchers will demonstrate the feasibility of 45-nanometer CMOS logic technology. The 45-nanometer measurement refers to the approximate width of the smallest feature on the silicon chip. The goal is to develop an SRAM (static RAM) chip made using the technology by 2005.

During the first phase, researchers will also begin research activities on 32- and 22-nanometer CMOS technologies.

The second phase of the NANOCMOS project, starting in 2006, will then demonstrate the feasibility of the 32- and 22-nanometer chip production processes. The goal is to develop chips using these technologies as early as 2007.

The plan also calls for this phase to become part of the Medea+ (Microelectronics Development for European Applications) project, a Europe-wide initiative focused on pre-competitive research in the area of semiconductors.

By 2006, the consortium of companies and research institutes in the NANOCMOS project hopes to use 45-nanometer technology in an industrial 300-millimeter wafer fabrication facility in Crolles, France. The wafer fab, called Crolles2, is operated by Koninklijke Philips Electronics NV and STMicroelectronics NV — both members of the NANOCMOS project — as well as Motorola Inc.

Other members of the project include Infineon Technologies AG, eight research labs coordinated by the French National Scientific Research Center and another three by the German research institute Fraunhofer Gesellschaft. The Commission lists a total of 12 organizations in the research initiative and expects more to sign up.

“This is the type of research that requires lots of minds to work together,” said Hannes Luyken, director of the project within Munich-based Infineon. “But it’s all pre-competitive research. So you’ll see us working with our partners, like IBM Corp., to develop our own 45-nanometer technology based on this fundamental research. The same applies for Philips, STM and Motorola, which are also collaborating in this area.”

Funding from the Commission could always be more, but it is nonetheless sufficient to stimulate industry participation in this area of chip production, Luyken said.

“Many companies and organizations have been forced to cut funds for fundamental research, so we are glad to see this commitment from the European Commission,” he said.

In addition to the NANOCMOS project, the Commission has agreed to sponsor a “network of excellence,” called SINANO. The aim of the networking initiative is to bring together all Europe research centers that could contribute, in some way, to the development of silicon-based devices on the scale of one to 40 nanometers.