TSMC to begin 65-nanometer production in December

Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest contract chip maker, plans to begin producing chips using a more advanced 65-nanometer manufacturing process starting in December, and will have a 45-nanometer process ready in 2008, the company said Wednesday.

The company will also offer an 80-nanometer manufacturing technology process “very soon,” said J.H. Tzeng, head of media relations at TSMC.

Switching to a more advanced production process allows chip makers to produce semiconductors that consume less power, perform faster, and cost less because they can be smaller in size.

Currently, TSMC’s most advanced technology used for commercial chip production is the 90-nanometer technology. The reference to size used to describe a chip-making process refers to the average feature size on a chip built using that process. One nanometer is one-billionth of a meter.

TSMC has been working on the shift to the 65-nanometer process for some time now. The company produced its first chip, an SRAM (synchronous RAM) chip with more than 100 million transistors, using the 65-nanometer process in April 2004. Over the last year, several TSMC customers, including programmable logic chip maker Altera, have had prototypes of their products produced using the 65-nanometer technology, the Hsinchu, Taiwan, chip maker said.

The 80-nanometer process will allow chip designers to save money while improving performance on semiconductors, as they move toward 65-nanometers. For the past few years, TSMC has offered customers a “half-node” shrink, to ease the transition to a new technology. The 90-nanometer to 65-nanometer transition costs millions of dollars in design work to complete. But a half-node shrink, like 80-nanometer, or previously 110-nanometer, allows companies to make slight alterations to existing designs, while gaining cost reductions and better chip performance.

Chips made using the 80-nanometer node, for example, could be around 20 percent speedier than chips made using the 90-nanometer process, Tzeng said. Because of the reduced size, companies will also gain around 20 percent more 80-nanometer technology chips from each silicon wafer run through the manufacturing process, helping lower costs.

TSMC will produce chips using the 65-nanometer process technology at two chip fabrication plants in Taiwan, Fab 12 and Fab 14, which use 300-millimeter silicon wafers. Fab 12 is located in Hsinchu and Fab 14 is in Tainan.