IBM combines strained silicon, SOI for fast transistors

By combining two semiconductor manufacturing techniques, IBM Corp. will improve transistor performance by about 50 percent in the next three to five years, the company said Tuesday.

The two techniques, strained silicon and silicon on insulator (SOI), have been brought together for the first time in a technique called strained silicon directly on insulator (SSDOI), IBM said. Additionally, IBM has developed another way to increase transistor performance by combining different substrates on a single wafer, said Meikei Ieong, senior manager of exploratory device and integration at IBM Research.

In order to keep increasing the speeds at which current flows through a chip, designers have come up with different ways to reduce power leakage and increase the mobility of electrons within a circuit. One such technique currently in use is SOI, which adds a thin oxide layer to a silicon wafer in order to insulate the circuit against power leakage.

Advanced Micro Devices Inc. (AMD) currently uses this technique in building its Opteron server processor, and IBM has also used the technique for a few years.

Strained silicon, which is expected to appear on Intel Corp.’s 90-nanometer chips, is a technique where a layer of silicon germanium is deposited on top of a silicon wafer, stretching the silicon atoms to allow electrons to flow faster through a circuit.

IBM’s new research allowed the Armonk, New York, company to use a layer transfer technique to apply both SOI and strained silicon to the same silicon wafer, Ieong said.

Researchers created a layer of strained silicon on top of a layer of silicon germanium, and then added an oxide layer atop that structure. That structure was then flipped over and placed on top of a second silicon wafer. This allowed researchers to remove the layer of silicon germanium at the end of the process, Ieong said.

By removing that layer of silicon germanium, IBM can improve the thermal conductivity of the wafer and eliminate a foreign material from the manufacturing process that adds complexity, he said.

This technique won’t be ready for production chips for another three to five years, Ieong said. It might make its debut on IBM’s 65nm process technology, he said.

The other manufacturing technique announced by IBM Tuesday mixes the surface orientations favored by different types of transistors on a single wafer, Ieong said.

Traditionally, chip-making companies have manufactured silicon wafers that favor only negatively charged transistors. Designers had to choose whether or not to optimize their substrates for negatively charged transistors or positively charged ones, and since they could get better overall performance out of a wafer optimized for a negatively charged transistor, that’s the way the chips were manufactured.

So in every chip, the negative transistors ran at optimal performance, but the positive transistors were not optimized. IBM has now developed a way to layer the substrate material that favors the positive transistors below the surface of the wafer that favors the negative transistors, Ieong said. IBM then punches holes in the surface in order to bring the positive transistor substrate to the surface of the wafer, Ieong said.

This means the wafer surface has a mixed orientation that favors both positive and negative transistors, and improves overall chip performance by between 40 percent and 65 percent, Ieong said. This technique could be implemented on IBM’s 90nm process technology, but probably won’t be ready for full production volumes for another three to five years, he said.