Reaching for gold

IN A DARING bid to wrest a larger share of the enterprise systems market from leaders IBM and Sun Microsystems, Intel is revamping its entire line of high-end CPUs, support chipsets, and server building blocks. This ambitious plan reworks Intel’s 32-bit and 64-bit processor technology to boost performance, enhance scalability, reduce power consumption, and ease integration. In 2002 and 2003, Intel plans to roll out eight new enterprise CPU models targeted at multiprocessor servers and workstations.

Intel hopes this flood of new technology will rouse the sleepy PC server market, but that’s not the company’s only goal. Intel wants a foothold in the burgeoning high-density server space. Through careful product positioning and counseling of OEMs, Intel will try to stem the use of less expensive (and lower margin) workstation hardware in server applications. Highly manageable, performance-tuned additions to Intel’s 64-bit CPU line will help eradicate the “Wintel” stigma that Unix rivals use as a sales tool. Intel also will lobby ISVs to optimize enterprise applications for Intel’s new architectures, giving customers a powerful incentive to upgrade and a reason to harbor reservations about Intel-compatible processors from AMD.

Can’t stray too far

Intel’s chief competitor in the enterprise server market, Sun Microsystems, regularly phases out support for retired architectures. It’s good business for Sun, because it shortens the time between upgrades and lowers support costs. By contrast, Intel’s desktop paradigm of “leave no customer behind” has contributed to the decline in profitability of PC servers. It has also forced software vendors to trade performance for compatibility. Most will not optimize applications for newer Intel CPUs. At some point, Intel, system OEMs, and ISVs will have to force periodic upgrades in the same way Unix vendors do.

The 32-bit Xeon processors on Intel’s enterprise road map are based on Pentium 4 Netburst technology. The Netburst Xeon’s cache memory is integrated into the CPU core rather than implemented as separate components, so cache latency (the time it takes the CPU to access data from the cache) is reduced. Increased circuit density –an etched “wire” in the Xeon is now just .13 microns wide — shrinks the the CPU, reduces manufacturing costs, and makes it easier to cool the processor. Intel made some architectural trade-offs to raise the Xeon’s maximum clock speed beyond the previous Pentium III design. At the same clock speed, a Pentium III CPU can outperform a Pentium 4 in some tasks. But the first batch of Netburst Xeons runs at a blistering 2.2GHz, more than twice the top speed of the Pentium III Xeon.

New instructions in the Netburst architecture accelerate the complex computations for high-resolution 2-D and 3-D graphics, scientific visualization, cryptography, and the like. Such demanding algorithms are increasingly finding their way into commonly used software. Another Netburst Xeon feature called hyperthreading speeds task switching by maintaining two sets of processor state information in the CPU’s fastest circuits (see ” Seeing double? ” Feb. 25). Intel ingeniously sidestepped compatibility issues by making each hyperthreaded Xeon masquerade as a pair of independent processors. This imparts a performance improvement to all multithreaded applications without requiring code changes. Still, to derive the maximum benefit from the Netburst architecture, applications should be optimized to use its unique features.

Intel has been slow to develop new enterprise chipsets, the hardware that connects CPUs to other system components. The Netburst Xeon is accompanied by a radically new Intel chipset, dubbed E7500, which raises the speed of the system’s bus (the CPU’s pathway to memory and peripherals) from 133MHz to 400MHz. Systems built with the E7500 chipset will use cheap, plentiful DDR (double data rate) RAM instead of the Rambus memory peculiar to recent Intel platforms. By interleaving memory accesses between a pair of independent channels, the E7500 doubles DDR’s native bandwidth to 3.2GBps. The chipset also increases the number of 64-bit PCI peripheral slots and implements the PCI-X bus standard.

The mature Pentium III processor has a new lease on life in ultradense servers. The 800MHz Pentium III isn’t terribly fast on its own — the idea is to mount a pair of these low-power, low-heat CPUs on a compact circuit card and stuff insane numbers of these “blade” cards into specialized servers.

Itanium gets serious

Intel shipped the first model of the Itanium 64-bit processor last year without fanfare. The new Itanium, code-named McKinley, is a huge step forward. Without requiring changes to existing 64-bit Intel applications (not that there are many of those), Intel expects McKinley to run 50 percent to 100 percent faster than the first-generation Itanium. Performance will improve further if applications are optimized for the new architecture. The first McKinley will appear midyear with a clock speed of 1GHz and 3MB of Level 3 cache. The bus interface implemented by the new Intel 870 chipset is three times faster than that of the first-generation Itanium. McKinley also has a faster, larger Level 2 cache.

As with Netburst Xeons, Intel’s reworked Itanium platform uses DDR memory and supports PCI-X peripherals. Three future generations of Itanium, all slated for introduction in 2003, will give customers high-performance and high-value alternatives to McKinley while maintaining software compatibility. Most of the future Itaniums will use the same chipset and system interface as McKinley, giving customers the uncommon advantage of upgrading their servers’ CPU architecture without replacing entire systems.

Intel is rounding out its enterprise strategy with new server building blocks architecture-optimized C/C++ and Fortran compilers, and an intense focus on server manageability. These advances, combined with substantial improvements to Intel’s 32-bit and 64-bit processor technology, should give Intel’s hungry OEMs a shot at a larger share of the enterprise pie.