ARM offers new protocol for more efficient chips

SAN JOSE, CALIFORNIA – An improved set of rules for communication among the different parts of a chip, unveiled Tuesday by ARM, could help make the chips at the heart of mobile phones and other devices smaller and faster.

At the Embedded Processor Forum in San Jose, California, ARM announced AMBA 3.0, the update to its AMBA (Advanced Microcontroller Bus Architecture) specification. With AMBA 3.0, the Cambridge, England, chip architecture provider added a new protocol, called AXI (AMBA Extensible Interface). The new protocol was designed primarily to pave the way to the next generation of high-performance SoC (system on a chip) designs. It was developed through collaboration with many major chip vendors, including Hewlett-Packard, Qualcomm, Toshiba and Ericsson Mobile Platforms. It is the successor to AMBA 2.0, introduced in 1999 and widely used in chips for mobile phones, PC hard disk drives, home networking equipment and many other products.

A system on a chip is a single processor that combines many different elements. AXI describes a way to make those elements communicate faster and more efficiently, allowing for SoCs of smaller size, less power consumption, higher performance or a combination of all three. A key step that made this possible was a unidirectional channel architecture, in which all information flow on the chip is in one direction only, said Jonathan Morris, platforms program manager at ARM.

For chip vendors, this architecture makes it simple to design and test a new chip, Morris said. It also will let some companies move from many different types of internal buses on their chips to one design, lowering their development costs, he added. For users of devices based on AXI, it is likely to mean faster chips. The new approach adds a slight latency, or delay, but pays off by allowing for a higher clock rate, he said.

AXI also lets a chip execute multiple transactions at the same time, Morris said. That could mean a chip can handle more functions at once or that it can finish a task more quickly and then go to sleep, reducing power consumption.

The new protocol should make it possible for embedded chips to process high-bandwidth streams of packets quickly, reducing the need for memory, according to Peter Glaskowsky, a principal analyst at In-Stat/MDR, which organized the conference. That will be necessary as networks get faster and devices have to handle richer applications such as multimedia, he said. It becomes possible with internal data buses that can deal with data streams quickly and at a predictable rate, so the chip doesn’t have to set aside data in a buffer.

Without more efficient buses, memory buffers would have to get bigger as network speeds go up. Those buffers are made up of transistors, which take up space and consume power on an SoC.

“A fast, predictable bus doesn’t take up any more space on a chip than a slow, unpredictable bus,” Glaskowsky said, whereas more memory does.

AXI is available to chip developers now through a free license and can be downloaded from ARM’s Web site at www.arm.com. Chip vendors that collaborated in AXI’s development already have the technology and some are now designing chips that use it, Morris said. Products based on chips built with AXI should hit the market next year, according to ARM.