It says here that AMD has released the the SSE5 specification. These instructions will appear in future x86 processors based on AMD's 64-bit Bulldozer core. Here's the AMD overview: With the introduction of SSE5, many new 128-bit instructions have been added to the existing instruction set detailed in the AMD64 Architecture Programmer's Manuals. Included are 46 base instructions that expand to 170 total ins Here’s the AMD overview: With the introduction of SSE5, many new 128-bit instructions have been added to the existing instruction set detailed in the AMD64 Architecture Programmer’s Manuals. Included are 46 base instructions that expand to 170 total instructions, enabling improved performance and reduced loads. New instructions include: Fused multiply accumulate (FMACxx) instructions Integer multiply accumulate (IMAC, IMADC) instructions Permutation and conditional move instructions Vector compare and test instructions Precision control, rounding, and conversion instructions Download the full document to learn about new three-operand instructions, a new 128-bit media instruction format, and more. Please send feedback to: SSE5.feedback@amd.com. » AMD64 Technology 128-Bit SSE5 Instruction SetWhat’s unusual about this instruction set is that AMD has published it on their own. More often, AMD says “Me, too” to new Intel instruction sets. The question is whether you should care about this as a software developer. If you maintain operating systems, drivers, libraries, or compilers that support AMD64 processors, you really should care about this, and start thinking about how you’ll integrate this instruction set into your products. If you develop applications in a high-level language, you probably will never want to bother to learn this instruction set. On the other hand, there’s an opportunity here for people who write specific kinds of image- and sound-processing applications to speed up their code. Is is time for more people to get their hands dirty with assembly language? Does your application use SIMD effectively? Would it be faster and better if it did? Would it help the computers that run it do more, stay cooler, and use less energy if it did? By the way, the SSE4 specification from Intel is here. SSE4 will be available in future processors based on the Penryn and Nehalem cores, and SSE4.1 will be available on future processors based Nehalem cores. Software Development